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The random access 1026 X 1026 imager above was designed to facilitate sub-array read out to minimized data rate and system overhead, while being able to update the sub-array information at a much higher frame rate than otherwise possible. For example, if a 5 X 5 sub array is read at a pixel rate of 1.0 MHz that sub-array can be read over 20,000 frames per second. Sub-array read out is accomplished by loading in the X and Y start address of the sub-array to the on chip preloadable up/down counters, then using a single element rate clock to advance the Y address counter to select the pixels along the row. When the desired number of pixels have been read along the row, the Y counter is preloaded again to the beginning sub array address and a single horizontal sub-array clock is used to clock the X address counter for the next line of the sub-array to be read. The process is repeated for the number of rows that exist for the desired size of the sub-array.

The on chip counter allows this random access imager to clock itself sequentially with a single very low power element rate clock if desired.

This array allows on chip charge manipulation at the pixel site. The charge collected at the pixel site can be read non-destructively (a.k.a. NDRO), to allow further integration of signal, the reduction to temporal noise, and/or signal "knock down." "Knock down" is the process of sensing the signal and making the determination that signal at a given pixel site will saturate before the next read will take place. Knock down is a method of extending dynamic range. A portion of the signal is then injected to maintain a linear response of the pixel(s) during the next integration period.

On chip random binning is facilitated on the random access 1026 X 1026 as each row and column has a one bit latch that allows for accumulation of multiple pixel addresses. When the selected pixels are simultaneously read, the charge from all selected pixels are summed together on one video port. This can be used to minimize data rates, randomly alter the resolution of the imager as desired, or to accomplish image reordering.

This imager design example demonstrates how CMOS allows the high level of integration of system level electronics onto the imager itself, thereby shrinking the size, power and cost of the imaging system while taking advantage of all the capabilities CMOS imagers provide.


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